Hello! I am a member of the Intel Graphics Compiler (IGC) team and I work on the design of compiler back-end/finalizer that performs local optimizations, register allocation and instruction scheduling to generate the final instructions for the target Intel GPU.
Prior to Intel, I was a hardware engineer at AMD, Austin working in the Data Fabric team. Prior to AMD, I was a PhD student at the University of Waterloo, Canada working on timing predictable and high-performance computer architecture with Professor Hiren Patel.
(C: Conference, J: Journal)
Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren Patel at CASES: ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (part of ESWEEK)
Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Anirudh Mohan Kaushik and Hiren Patel in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Extension of (C9)
Anirudh Mohan Kaushik and Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Zhuanhao Wu, Anirudh Mohan Kaushik, Paulos Tegegn, Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Anirudh Mohan Kaushik, Gennady Pekhimenko, Hiren Patel in ACM Transactions on Architecture and Code (TACO)
Anirudh Mohan Kaushik and Hiren Patel in IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE)
I enjoy listening to Indian classical and Jazz music, reading books on history, and swimming.