Hello! I am an Assistant Professor (Tenure track) in the Electrical Engineering and Computer Science (EECS) department at Lassonde School of Engineering, York University, Canada. I joined the department in January 2025. I received my Ph.D. from the University of Waterloo, Canada in 2021, where I worked with Professor Hiren Patel. My research interests span both computer hardware and software for cyber-physical systems (CPS) and high-performance systems. Currently, my main research focuses on designing multi-core and many-core compute systems for CPS that achieve both timing-predictability and high-performance. My research statement provides an in-depth description of my prior research and research vision.

Prior to joining YorkU, I was a compiler engineer in Intel where I worked on the Intel Graphics Compiler (IGC), and a hardware engineer at AMD where I worked on the Data Fabric interconnect IP.

CV

Research Statement

Teaching Statement

Diversity Statement

Teaching

[Winter 2025] ECE 4201Z – Computer Architecture

Recent Publications

(C: Conference, J: Journal)

2024

(J5) High Performance and Predictable Shared Last-Level Cache for Safety-Critical Systems

Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren Patel in ACM Transactions on Embedded Computing Systems. Extension of (C12)

2023

(C13) Predictable GPU Wavefront Splitting for Safety-Critical Systems

Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren Patel at CASES: ACM International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (part of ESWEEK)

(C12) ZeroCost-LLC: Shared LLCs at No Cost to WCL

Zhuanhao Wu, Anirudh Mohan Kaushik, Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

2022

(J4) Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multicore Real-Time Systems

Anirudh Mohan Kaushik and Hiren Patel in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Extension of (C9)

2021

(C11) A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence

Anirudh Mohan Kaushik and Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

(C10) A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores

Zhuanhao Wu, Anirudh Mohan Kaushik, Paulos Tegegn, Hiren Patel at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

(J3) Gretch: A Hardware Prefetcher for Graph Analytics

Anirudh Mohan Kaushik, Gennady Pekhimenko, Hiren Patel in ACM Transactions on Architecture and Code (TACO)

(C9) Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols

Anirudh Mohan Kaushik and Hiren Patel in IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE)

Older publications (2020 and prior), dissertation, and thesis

Miscellaneous

I enjoy listening to Indian classical and Jazz music, reading books on history, and swimming.