Anirudh Mohan Kaushik
GPU Compiler engineer at Intel Canada. Research and development in GPU compiler backend. PhD in Computer Engineering from UWaterloo.
Publications (pre-2020)
2020
(J2) Designing predictable cache coherence protocols for multi-core real-time systems
Anirudh Mohan Kaushik, Mohamed Hassan, Hiren Patel in IEEE Transactions on Computers (TC) Extension of C5
2019
(C8) CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems
Anirudh Mohan Kaushik, Paulos Tegegn, Zhuanhao Wu, Hiren Patel in IEEE Real-Time Systems Symposium (RTSS)
(C7) Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems
Nivedita Sritharan, Anirudh Mohan Kaushik, Mohamed Hassan, Hiren Patel in IEEE Real-Time Systems Symposium (RTSS)
(C6) Optimizing Hyperplane Sweep Operations Using Asynchronous Multi-grain GPU Tasks
Anirudh Mohan Kaushik, Ashwin M Aji, Muhammad Amber Hassaan, Noel Chalmers, Noah Wolfe, Scott Moe, Sooraj Puthoor, Bradford M Beckmann in IEEE International Symposium on Workload Characterization (IISWC)
2018
(J1) Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis
Mohamed Hassan, Anirudh Mohan Kaushik, Hiren Patel in ACM Transactions on Embedded Computing Systems (TECS)
2017
(C5) Predictable cache coherence for multi-core real-time systems
Mohamed Hassan, Anirudh Mohan Kaushik, Hiren Patel in IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
2015
(C4) Reverse-engineering embedded memory controllers through latency-based analysis
Mohamed Hassan, Anirudh Mohan Kaushik, Hiren Patel in IEEE Real-Time and Embedded Technology and Applications Symposium
2013
(C3) Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models
Anirudh Mohan Kaushik and Hiren Patel in IEEE Proceedings of Forum on specification and Design Languages (FDL)
(C2) On the use of GP-GPUs for accelerating compute-intensive EDA applications
Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh Mohan Kaushik, Hiren D Patel in IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE)
2012
(C1) Accelerating SystemC simulations using GPUs
Mahesh Nanjundappa, Anirudh Mohan Kaushik, Hiren D Patel, Sandeep K Shukla in IEEE International High Level Design Validation and Test Workshop (HLDVT)